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High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
Revision History
Rev. No. 2.0
History Initial issue with new naming rule
Issue Date Dec.29,2004
Remark
1
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
GENERAL DESCRIPTION
The CS18LV02565 is a high performance, high speed and super low power CMOS Static Random Access Memory organized as 32,768 words by 8bits and operates for a single 4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 55/70ns in 5.0V operation. Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE). The CS18LV02565 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV02565 is available in JEDEC standard 28-pin TSOP I (8x13.4 mm), SOP (330 mil) and PDIP (600 mil) packages.
FEATURES
Wide operation voltage : 4.5 ~ 5.5V Ultra low power consumption : 2mA1MHz (Max.) , Vcc=5.0V. 1.0 uA (Typ.) CMOS standby current High speed access time : 55/70ns. Automatic power down when chip is deselected. Three state outputs and TTL compatible. Data retention supply voltage as low as 1.5V. Easy expansion with /CE and /OE options.
PRODUCT FAMILY
Product Family Operating Temp. Vcc Range Speed (ns) Standby Current(Typ.)
ICCSB1
1.0 uA (Vcc = 5.0V)
Package Type 28 SOP
0~70oC
55/70
28 TSOP I 28 PDIP Dice 28 SOP
CS18LV02565
4.5~5.5V 1.5 uA (Vcc= 5.0V)
-40~85oC
55/70
28 TSOP I 28 PDIP Dice
2
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2
PIN CONFIGURATIONS
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14
28TSOP(I)-8x13.4mm
FUNCTIONAL BLOCK DIAGRAM
A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0
Address Input Buffer
18
Row Decoder
512
Memory Array 512x512 512
8
Data Input Buffer Data Output Buffer
8
Column I/O
DQ7
8
8
Write Driver Sense Amp 64 Column Decoder
/CE /WE /OE VCC GND
Control
12 Address Input Buffer A0 A1 A2 A3 A4 A10
3
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
Function
PIN DESCRIPTIONS
Name
A0 - A14
Type
Input
Address inputs for selecting one of the 32,768 x 8 bit words in the RAM /CE is active LOW. Chip enable must be active when data read from or write
/CE
Input
to the device. If chip enable is not active, the device is deselected and in a standby power mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write operations.
/WE
Input
With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the
/OE
Input
chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive.
DQ0~DQ7 Vcc Gnd
I/O Power Power
These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
TRUTH TABLE
Mode
Standby Output Disabled Read Write
/CE
H L L L
/WE
X H H L
/OE
X H L X
DQ0~7
High Z High Z DOUT DIN
Vcc Current ICCSB, ICCSB1
ICC ICC ICC
4
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
Rating
-0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM TBIAS TSTG PT IOUT
Parameter
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Unit
V
O O
C C
W mA
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial Industrial
Ambient Temperature
0~70 C -40~85oC
o
Vcc
4.5~5.5V 4.5~5.5V
CAPACITANCE(1)(TA=25,f=1.0MHz)
Symbol
CIN CDQ
Parameter
Input Capacitance Input/Output Capacitance
Conduction
VIN=0V VI/O=0V
MAX.
6 8
Unit
pF pF
1. This parameter is guaranteed, and not 100% tested.
5
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
( TA = 0 ~70 C, Vcc = 5.0V)
o o
DC ELECTRICAL CHARACTERISTICS
Name VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1 Parameter
Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current TTL Standby Supply CMOS Standby Current
Test Condition
Vcc=5.0V
MIN
-0.5
TYP(1)
MAX
1.5
Unit
V
Vcc=5.0V VCC=MAX, VIN=0 to VCC VCC=MAX, /CE=VIN, or /OE=VIN , VIO=0V to VCC VCC=MAX, IOL = 1mA VCC=MIN, IOH = -1mA /CE=VIL, IDQ=0mA, F=FMAX =1/ tRC /CE=VIH, IDQ=0mA, /CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V,
2.5 -1 -1
Vcc+0.2 1 1 0.4
V uA uA V V
2.2 20 1 1.0 4
mA mA uA
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
DATA RETENTION CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
Name
VDR
Parameter
VCC for Data Retention
Test Condition
/CE VCC-0.2V, VIN VCC-0.2V or VIN0.2V
MIN TYP(1) MAX
1.5
Unit
V
ICCDR
Data Retention Current
/CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V
0.5
3
uA
TCDR tR
1. TA = 25 C.
o
Chip Deselect to Data Retention Time Operation Recovery Time
Refer to Retention Waveform
0 tRC (2)
ns ns
2. tRC= .Read Cycle Time.
6
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
Vcc CE
tCDR VIH
Data Retention Mode VDR >= 1.5V CE >= VCC - 0.2V
tR VIH
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns
KEY TO SWITCHING WAVEFORMS
WAVEFORMS INPUTS OUTPUTS
MUST BE STEADY MUST BE STEADY
0.5Vcc
MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED DOES NOT APPLY
WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE OFF STATE
AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
7
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V ) < READ CYCLE >
JEDEC Name tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX Symbol tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Description
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Address Change to Out Disable 10 10 ns 0 30 0 30 ns 0 35 0 35 ns 10 5 10 5 ns ns
-55
MIN 55 55 55 30 MAX 70
-70
MIN MAX
Unit
ns
70 70 50
ns ns ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC ADDRESS tOH DOUT tAA tOH
8
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
READ CYCLE2 (1,3,4)
CS18LV02565
READ CYCLE3 (1,4)
tRC ADDRESS tAA OE tOE CE tOLZ tCLZ (5) DOUT tCE tCHZ (5) tOHZ (1,5) tOH
NOTES: 1. /WE is high in read Cycle. 2. Device is continuously selected when /CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. /OE = VIL. 5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse levels of 0V to VCC and output loading specified in Figure 1A. 6. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
9
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V ) < WRITE CYCLE >
JEDEC Name tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHOX Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW Description
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold for Write End Output Disable to Output in High Z End of Write to Output Active 5 5 ns 20 0 0 30
-55
55 55 0 55 40 0 25 30 0 0 70 70 0 70 50 0
-70
MIN MAX MIN MAX
Unit
ns ns ns ns ns ns
35
ns ns ns
30
ns
10
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
WRITE CYCLE2 (Chip Enable Controlled)
11
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit NOTES:
1. 2. /WE must be high during address transitions. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. 4. 5. 6. TWR is measured from the earlier of /CE or /WE going high at the end of write cycle. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state. /OE is continuously low (/OE = VIL ).DOUT is the same phase of write data of this write cycle. 7. DOUT is the read data of next address. 8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse levels of 0V to VCC and output loading specified in Figure 1A. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of /CE going low to the end of write.
CS18LV02565
ORDER INFORMATION
12
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
PACKAGE DIMENSIONS
28 pin SOP (330 mil) :
SYMBOL UNIT Min. mm
A
A1
A2
b 0.35 _ 0.50
b1 0.35 _ 0.45
c 0.20 _ 0.32
c1
D
E
E1
e
L
L1
y _ _ 0.1 _ _ 0 _ 10 0 _ 10
2.540 0.102 2.362 2.489 2.616
Nom. 2.692 0.226 Max. 2.844 0.350 Min. 0.100 0.004
0.20 17.983 8.280 11.506 1.118 _ 18.110 8.407 11.811 1.270 0.28 18.237 8.534 12.116 1.422
0.700 1.520 0.964 1.720 1.228 1.920
inch
Nom. 0.106 0.009 0.098 Max. 0.112 0.014
0.093 0.014 0.014 0.008 0.008 0.708 0.326 0.453 0.044 0.0276 0.0598 _ _ _ _ 0.713 0.331 0.465 0.050 0.0380 0.0677 0.103 0.020 0.018 0.012
0.011 0.718 0.336 0.477 0.056 0.0484 0.0756 0.004
-
28 pin TSOP I (8x13.4 mm) :
12(2x) HD
cL
12(2x)
1
28
E b
e
Seating Plane
14 15 12(2X)
y
"A"
D GAUGE PLANE
A2 A
A 0
0.254
A1
14
15
SEATING PLANE
A 12(2X) L L1
"A" DATAIL VIEW b
WITH PLATING
1
28
c c1
BASE METAL
b1
SECTION A-A
SYMBOL UNIT Min. mm Max. inch A 1.00 1.20 A1 0.050 0.115 0.180 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 0.007 0.009 b1 0.17 0.20 0.23 0.007 0.008
c 0.10 _ 0.21 0.004 _ 0.008
c1 0.10 _ 0.16 0.004 _ 0.006
D 11.70 11.80 11.90 0.461 0.465 0.469
E 7.90 8.00 8.10 0.315 0.319
e 0.45 0.55 0.65 0.022 0.026
HD 13.20 13.40 13.60
L 0.40 0.50 0.70
L1 0.70 0.80 0.90
y _ _ 0.1 _ _ 0 _ 8 0 _ 8
Nom. 1.10
Min. 0.0393 0.0019 0.037 Nom. 0.0433 0.0045 0.039 Max. 0.0473 0.0071 0.041
0.311 0.018
0.520 0.0157 0.0275 0.528 0.0197 0.0315
0.011 0.009
0.536 0.0277 0.0355 0.004
13
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit 28 pin PDIP (600mil):
CS18LV02565
SYMBOL UNIT Min. mm A1 0.254 _ Nom. _ Max. 0.010 _ Nom. _ Max. Min. inch A2
B
B1
c
D
E
E1
e
eB
L
S
Q1 1.651 3 6 9 3 6 9
3.683 0.330 1.270 3.810 3.937 0.145 0.150 0.155 0.457 1.524 0.584 1.778 0.013 0.050 0.018 0.060 0.023 0.070
0.152 36.957 14.986 13.716
2.540 0.254 37.084 15.240 13.818 (TYP) 16.256 3.302 0.356 37.211 15.494 13.920 16.764 3.556 0.006 1.455 0.010 1.460 0.014 1.465 0.590 0.600 0.610 0.620 0.100 0.544 (TYP) 0.640 0.660 0.548 0.540 0.120 0.130
15.748 3.048 1.778
2.032 1.778 2.286 1.905 0.070 0.080 0.090 0.065 0.070 0.075
0.140
14
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.

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